独立中文 FPGA 技术专题与行业媒体https://myfpga.com.cn/zh-cnhttps://myfpga.com.cn/articles/domestic-fpga-ecosystem-guide/https://myfpga.com.cn/articles/domestic-fpga-ecosystem-guide/从器件、开发工具、IP、开发板、资料和供货支持认识国产 FPGA 生态，建立可核实的项目评估清单。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-architecture-basics/https://myfpga.com.cn/articles/fpga-architecture-basics/认识 LUT、触发器、片上存储、DSP、互连和时钟资源，并理解不同器件的资源命名与配置并不完全相同。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-board-bring-up-checklist/https://myfpga.com.cn/articles/fpga-board-bring-up-checklist/以分层检查方式开展 FPGA 板卡首次上电与调试，覆盖供电、JTAG 配置、时钟复位、I/O 和片上逻辑分析。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-clock-domain-crossing-basics/https://myfpga.com.cn/articles/fpga-clock-domain-crossing-basics/了解异步时钟域中的亚稳态风险，并区分单比特电平、事件脉冲和多位数据的跨域传递方式。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-combinational-and-sequential-logic/https://myfpga.com.cn/articles/fpga-combinational-and-sequential-logic/从组合逻辑、触发器与时钟沿理解 RTL 如何映射为硬件，并用 SystemVerilog 示例说明默认赋值和寄存器更新。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-configuration-and-bitstream-basics/https://myfpga.com.cn/articles/fpga-configuration-and-bitstream-basics/认识 FPGA 配置文件、JTAG 下载与非易失存储器启动之间的区别，并了解文件格式因器件系列而异。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-design-flow-introduction/https://myfpga.com.cn/articles/fpga-design-flow-introduction/了解 FPGA 项目中需求分析、RTL 设计、仿真、综合、布局布线、时序分析、配置文件生成与板级验证的基本关系。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-external-ddr-interface-basics/https://myfpga.com.cn/articles/fpga-external-ddr-interface-basics/从 FPGA 系统视角了解外部 DDR 接口中的控制器、物理层、初始化校准和板级约束。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-fifo-basics/https://myfpga.com.cn/articles/fpga-fifo-basics/了解 FIFO 如何缓冲数据流、如何估算容量，以及单时钟与双时钟 FIFO 的适用边界。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-finite-state-machine-basics/https://myfpga.com.cn/articles/fpga-finite-state-machine-basics/认识有限状态机的状态寄存器、下一状态逻辑和输出逻辑，理解 Moore 与 Mealy 输出及状态编码选择。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-fixed-point-and-bit-width-basics/https://myfpga.com.cn/articles/fpga-fixed-point-and-bit-width-basics/从补码与二进制小数理解定点运算，明确量化、舍入、溢出策略及加法、乘法、累加的位宽增长。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-i2c-interface-basics/https://myfpga.com.cn/articles/fpga-i2c-interface-basics/从开漏上拉理解 I²C 数据传输、ACK/NACK、重复起始和时钟延展，并建立 FPGA 实现与板级检查思路。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-introduction/https://myfpga.com.cn/articles/fpga-introduction/从可编程逻辑、并行电路和配置流程认识 FPGA，并了解它与处理器及 ASIC 的差异。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-on-chip-logic-analyzer-debugging/https://myfpga.com.cn/articles/fpga-on-chip-logic-analyzer-debugging/了解 AMD ILA 与 Intel Signal Tap 调试中的探针规划、采样时钟、触发和存储取舍，区分仿真、片上采样与外部示波器，并检查调试逻辑对实现的影响。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-on-chip-memory-basics/https://myfpga.com.cn/articles/fpga-on-chip-memory-basics/认识 FPGA 片上存储资源与 RAM 推断方式，了解端口、读写行为和综合报告对设计实现的影响。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-pcba-production-test-basics/https://myfpga.com.cn/articles/fpga-pcba-production-test-basics/了解 FPGA 板卡生产测试与 RTL 仿真的边界，并规划配置、板级功能、接口验证、工装和测试记录。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-pcie-data-transfer-and-debugging/https://myfpga.com.cn/articles/fpga-pcie-data-transfer-and-debugging/区分 PCIe MMIO 与 DMA 的用途，梳理 FPGA 数据路径、主机驱动协同及从链路到数据校验的调试顺序。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-pcie-endpoint-and-bar-basics/https://myfpga.com.cn/articles/fpga-pcie-endpoint-and-bar-basics/建立 PCIe Endpoint、链路宽度、配置空间与 BAR 的基础概念，区分链路建立、主机枚举和用户逻辑访问。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-pin-planning-and-io-constraints/https://myfpga.com.cn/articles/fpga-pin-planning-and-io-constraints/了解 FPGA 引脚分配如何与 PCB、I/O Bank、电压标准、时钟和差分接口协同规划。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-pipeline-throughput-latency/https://myfpga.com.cn/articles/fpga-pipeline-throughput-latency/用简短数据通路示例理解流水线寄存器划分、吞吐率与延迟，并认识反压、控制对齐和时序优化的取舍。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-power-estimation-and-thermal-design-basics/https://myfpga.com.cn/articles/fpga-power-estimation-and-thermal-design-basics/理解静态与动态功耗、时钟翻转和 I/O 负载，准备工具估算输入，并通过板级测量与散热验证区分模型结果和实际运行表现。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-rtl-simulation-testbench/https://myfpga.com.cn/articles/fpga-rtl-simulation-testbench/了解如何用 testbench 驱动 RTL 设计、检查预期行为，并理解仿真与板级验证之间的边界。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-spi-interface-basics/https://myfpga.com.cn/articles/fpga-spi-interface-basics/理解 SPI 主从角色与四种时钟模式，区分 FPGA 内部移位逻辑、引脚电气条件及板级时序验证。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-timing-constraints-basics/https://myfpga.com.cn/articles/fpga-timing-constraints-basics/从时钟、输入输出延迟和关键路径认识 FPGA 时序约束，并了解如何阅读静态时序分析结果。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/articles/fpga-uart-interface-basics/https://myfpga.com.cn/articles/fpga-uart-interface-basics/理解 UART 波特率采样与收发状态机，明确逻辑电平 UART、RS-232 和 RS-485 的边界及板级验证方法。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/news/fpga-application-landscape/https://myfpga.com.cn/news/fpga-application-landscape/以应用场景了解 FPGA 的常见使用方向，并从实时性、接口、可更新性和工程生态评估是否适合项目。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/news/fpga-industry-ecosystem-overview/https://myfpga.com.cn/news/fpga-industry-ecosystem-overview/从芯片设计、开发工具和 IP，到板卡、系统集成与终端应用，梳理 FPGA 项目的产业协作关系。Mon, 05 Oct 2026 00:00:00 GMThttps://myfpga.com.cn/resources/fpga-project-evaluation-checklist/https://myfpga.com.cn/resources/fpga-project-evaluation-checklist/用一份可复用清单梳理 FPGA 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